Semiconductor Engineering: Observability Is A Missing Layer In AI-Era Chiplet Design
8.14.2026
Originally published on Semiconductor Engineering by Ann Mutschler | July 1, 2026.
Semiconductor Engineering convenes an Experts At The Table roundtable on in-silicon observability, featuring Satish Radhakrishnan, head of GTM at Vinci, alongside panelists from Arteris, Axiomise, Baya Systems, Cadence, Keysight EDA, Movellus, Siemens EDA, and Synopsys. The discussion covers how AI is being applied to silicon telemetry and what it takes to scale observability across multi-die and chiplet architectures.
The panel examines where AI is genuinely being used today across collection, analysis, and action — and where it isn’t. Radhakrishnan describes AI’s growing role across design, verification, and simulation, and points to the shift from reactive to predictive engineering as models are continually trained to recognize subtle patterns such as data degradation before they become failures.
Asked how observability scales in chiplet architectures, Radhakrishnan argues the answer requires a pre-trained system that can simulate the full complex design extremely fast without compartmentalizing it, because crosstalk and interactions happen across the whole assembly. He also raises secure, standardized communication between components from different companies as a prerequisite for AI-driven decision-making, noting that issues like cracks and hotspots propagate across chips through crosstalk.
"You need to be able to take everything as a whole."
Key takeaways from the coverage:
Vinci’s Satish Radhakrishnan argues that scaling observability requires speed, accuracy, and system-level scope together — analysis that cannot be compartmentalized die by die.
Crosstalk and physical interactions across a package mean faults such as cracks and hotspots affect multiple chips, requiring whole-system rather than isolated analysis.
Semiconductor Engineering reports broad agreement across the panel that scaling observability is fundamentally an architectural and standards problem, with AI dependent on the structure underneath it.
Panelists identify secure telemetry schemas and multi-vendor standards as prerequisites for a viable merchant chiplet ecosystem.
How does this relate to Vinci's platform?
The roundtable’s central tension — that AI can only interpret what the architecture makes visible — maps directly onto Vinci’s approach to physics. Telemetry tells engineers what happened; deterministic, full-resolution physics tells them why it happened and what will happen next, at the level of real geometry rather than approximation.
For chiplet and advanced packaging teams, that means thermal and thermo-mechanical behavior can be evaluated across the full assembly, spanning die, package, and interconnect domains, while designs are still changing — closing the gap between in-field observability and the design decisions that determine reliability in the first place.
About Vinci
Vinci is a frontier lab building the foundation model for the physical world. Its deterministic, solver-grounded systems make physics continuously computable inside production engineering workflows and are already running on flagship programs, shifting physics from an episodic simulation bottleneck to continuous infrastructure for design, manufacturing, and reliability decisions.
